Micron Technology is now using AMD’s newly announced third-generation Epyc server CPUs to power most of its high-demand applications for designing memory and storage chips.
Ram Peddibhotla, AMD’s corporate vice president of Epyc product management, told The Register last week about Micron’s decision, and a spokesperson for Micron later confirmed to us that it moved “most of its most demanding” electronic design automation applications to servers with AMD’s CPUs last year.
“They have a state-of-the-art, high performance architecture for EDA to get them to design their products [and] maximize productivity for their designers,” he said.
This allowed Micron to improve EDA performance by 30 percent, and it also lowered the combined upfront and ongoing costs for running datacenters, according to Peddibhotla.
He added that Micron is now testing servers with AMD’s new Epyc “Milan-X” processors — which were officially released on Monday — and found that they provide an additional 40 percent performance boost over last year’s third-gen EPYC chips on select EDA workloads thanks to the CPU’s large 768MB of L3 cache.
“It was really, really good with [AMD’s third-gen Epyc] and getting even better with Milan-X,” he said.
Micron did not say which CPU architecture the company previously used for its EDA datacenters, but what’s notable to us is that the company did not choose Intel’s latest Xeon processors, which is understandable if AMD’s latest performance comparisons are reliable. A major supplier of memory and storage technologies, Micron brought in $27.7bn in revenue last year. ®
Peddibhotla said the move is part of a “long-running collaboration” between chipmaker and Micron, which also includes validating AMD’s products on Micron’s DDR5 memory and SSD technologies.
“Micron and AMD share a vision of delivering full capability of leading DDR5 memory to high-performance datacenter platforms,” said Raj Hazra, a former Intel executive who now leads Micron’s Compute and Networking Business Unit, in a canned statement.
Launched on Monday, AMD’s new Epyc Milan-X chips pack a massive 768MB of L3 cache thanks to the company’s new 3D V-Cache technology that allowed the chipmaker to triple the L3 for every group of cores on the processor, also known as the core complex die. The chipmaker said this has a major impact on cache-sensitive applications, namely technical computing workloads like EDA. ®