AMD says it is well on its way to achieving its ambitious goal to deliver a 30-fold increase in energy efficiency across its high-performance compute (HPC) platforms by 2025.
In an update released Tuesday, CTO Mark Papermaster claimed the processor designer has already achieved a 6.79x efficiency gain in the eight months since the 30×25 initiative was announced.
The initiative seeks to dramatically reduce operating costs, preserve natural resources, and mitigate climate impacts, while simultaneously keeping up with demand for HPC and AI/ML workloads, Papermaster said in a statement.
Pushing the envelope of energy efficiency is nothing new for the House of Zen. Previously AMD set out to achieve a 25x improvement in mobile processor efficiency from 2014 to 2022. The company ultimately says it has surpassed that goal, claiming a 31.7x improvement.
To put the chip designer’s latest goal into perspective, a 30x efficiency gain on its 2020 baseline — an Epyc 7002 processor and Vega 20 Instinct MI150 GPU combo — will require AMD to curb the power consumption required to perform a single calculation by 97 percent.
“Getting there will not be easy. To achieve this goal means that we will need to increase the energy efficiency of an accelerated compute node at a rate that is more than 2.5x faster than the aggregate industry-wide improvement made during the period 2015-2020,” Papermaster wrote.
Achieving this goal could have a profound impact on the sustainability of modern datacenters, Papermaster wrote. “For example, if all global AI and HPC server nodes were to make similar gains, we project up to 51 billion kilowatt-hours of electricity could be saved from 2021-2025, relative to industry trends.”
This, AMD claimed, would amount to $6.2 billion in electricity savings.
AMD Instinct amps efficiency goals
Since announcing the initiative in September, the company claims it’s achieved a 6.79-fold improvement in efficiency from its baseline.
As promised, much of these gains were achieved through improvements to the company’s Instinct GPU accelerators — which received a significant update at AMD’s Accelerated Datacenter Event in November.
The aforementioned efficiency improvement this week involved a single third-generation AMD Epyc processor accompanied by four top-of-the-line MI250x GPUs, and were validated by power-efficiency guru John Koomey. He previously discussed bending the efficiency curves for supercomputing with our sister title, The Next Platform.
The MI250x is based on a twin-die architecture that packs 58 billion transistors using a 6nm manufacturing process. AMD claims the GPUs offer more than 1.8x the performance of its MI100-series chips.
AMD’s third-gen Epyc and MI250x are at the heart of America’s Oakridge National Laboratory’s 1.5 exaFLOP Frontier Supercomputer, which came online earlier this year.
Will Xilinx play a role?
Papermaster also alluded to the use of domain-specific processors — an entire portfolio of which it acquired with the $49 billion purchase of FPGA giant Xilinx that completed this year — in graphic captioned: “Application specific accelerated compute nodes enable greater efficiency.”
FPGAs — field programmable gate arrays — fit somewhere between a fixed-function ASIC and a general-purpose processor from, say, AMD or Intel. Their digital logic circuits can dynamically reconfigured — or, in other words, rearchitected — on the fly to accelerate domain-specific applications.
Xilinx is a titan of the FPGA market, and has large portfolio of products tailored to use cases including space travel, industrial systems, embedded electronics, telecommunications, and AI. Xilinx’s Alveo FPGAs are a likely candidate to aid AMD’s 30×25 goal. ®